The Jupiter 32-bit EISC
microcontroller is a cost-effective, high-performance
microcontroller solution for Ethernet-based systems. The
Jupiter is designed as an integrated two ethernet
controller for use in managed communication hubs and
routers. The Jupiter is built around an outstanding
CPU core: the 32-bit EISC processor designed by ADC. The
EISC SE3208 is a product in the EISC series and is
optimised for embedded applications and as a general
purpose 32bit high-performance microprocessor. The
resulting EISC possesses a higher code density
displaying CISC level performance and employs a reduced
instruction set to simplify hardware.
The Jupiter
offers a unified cache, ethernet controller , and STN
LCD controller to reduce total system costs. Important
peripheral functions include 2-channel UART, 2-channel
DMA, SIO controller, four 32-bit timers, and
programmable I/O ports. On-board logic consists of an
interrupt controller, DRAM controller, and a controller
for ROM/SRAM. The System Manager includes an internal
32-bit system bus arbiter and an external memory
controller.
Built in 32bit CPU and Cache -
High Performance EISC Core SE3208 - 2 Way Set
Associative Unified Cache with 4Kbyte. - Pseudo
LRU(Least Recently Used) Replace Algorithm. - Write
Through / Write Back Policy to Maintain the Coherence
between Main Memory and Cache Memory. - Write Buffer
with 4 Depth. - 50Mhz operation
Memory
management - 32Mbyte Address Space per each Bank.
- Support 8 Memory Banks and Another Memory Bank for
Debugging . - Supports External Wait Signal to
Expand The Bus Cycle. - Supports Asymmetric/Symmetric
Address of DRAM.
Clock Power
Management - On-chip PLL makes the clock for
operating MCU. - Supports PLL power down -
Supports slow mode for power down and low frequency
clock without PLL.
Ethernet
Controller - Integrated two ethernet
controller - DMA engine with burst mode - DMA
Tx/Rx buffers (256 bytes Tx, 256 bytes Rx) - MAC
Tx/Rx FIFO buffers (80bytes Tx, 16bytes Rx) - Data
alignment logic - Endian translation - 100/10-Mbit
per second operation - Full compliance with IEEE
standard 802.3 - MII and 7 wired 10 Mbps
interface - Station management signaling - On chip
CAM (up to 21 destination address) - Full duplex mode
with PAUSE feature - Long/short packet modes - PAD
ganeration
LCD Controller Supports
color/gray/monochrome LCD panels. Supports 3 types of
LCD panels: 4-bit dual scan, 4-bit
single scan, 8-bit single scan display type. Supports
Multiple Virtual Display Screen. (Supports Hardware
Horizontal/Vertical Scrolling) The system memory is
used as the display memory. Dedicated DMA supports to
fetch the image data from video buffer located in system
memory. Supports multiple screen
size. Typical actual screen sizes:
640x480, 320x240, 160x160
(pixels) Maximum virtual screen
sizes(color mode): 4096x1024, 2048x2048, 1024x4096,
etc Supports the monochrome, 4 gray levels, and 16
gray levels . Supports 256 level colors for color STN
LCD panel. Supports the power saving mode(SL_IDLE
Mode).
Peripheral functions - 2 Ch.
General DMA - 32 Ch. Priority Interrupt
controller - 4 Ch. 12 bit Counter for timer and Watch
Dog Timer - 1 Ch. Pulse Period
Measurement - 2 Ch. UART with 16 *
8 bit FIFO - 32 PIO (Peripheral Input Output) -
Max. 30 key scan - 1 Ch. Pulse width
moduation - Real Time
Clock - 1 Ch. Synchronous serial
IO
Process - 0.35um CMOS VLSI - 3.3
Volt Operation - 208 Pin TQFP Package
advanced digital chips inc. 4th Floor, Sam
Kwang Bldg. 21-4,Samsung-Dong, Kangnam-Ku, Seoul,
135-090 Korea Tel : 82-2-545-4484
Fax
: 82-2-545-4485 http://www.adc.co.kr
E-mail
: hlee@adc.co.kr
JUPITER 32-Bit EISC Microcontroller
